4 search results - page 1 / 1 » Using Launch-on-Capture for Testing Scan Designs Containing ... |
TCAD
2011
13 years 2 months ago
2011
—This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered launch-oncapture (LOC) scheme followed by the one-hot LOC scheme for testing ...
ENTCS
2008
13 years 7 months ago
2008
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...
ITC
2003
IEEE
14 years 25 days ago
2003
IEEE
When developing new designs, debugging the prototype is important to resolve application malfunction. During this board design debug, often a few pins of an IC are measured to che...
ARVLSI
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...