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VLSID
2002
IEEE
119views VLSI» more  VLSID 2002»
14 years 9 months ago
Reducing Library Development Cycle Time through an Optimum Layout Create Flow
One of the major roadblocks in reduction of library generation cycle time is the layout generation phase. The two methods of doing automatic layout generation are synthesis and mig...
Rituparna Mandal, Dibyendu Goswami, Arup Dash
SIGSOFT
1998
ACM
14 years 29 days ago
Reasoning about Implicit Invocation
Implicit invocation SN92, GN91] has become an important architectural style for large-scale system design and evolution. This paper addresses the lack of speci cation and veri cat...
David Garlan, Somesh Jha, David Notkin
GECCO
2006
Springer
154views Optimization» more  GECCO 2006»
14 years 12 days ago
Spectral techniques for graph bisection in genetic algorithms
Various applications of spectral techniques for enhancing graph bisection in genetic algorithms are investigated. Several enhancements to a genetic algorithm for graph bisection a...
Jacob G. Martin
ICDT
2001
ACM
147views Database» more  ICDT 2001»
14 years 1 months ago
Parallelizing the Data Cube
This paper presents a general methodology for the efficient parallelization of existing data cube construction algorithms. We describe two different partitioning strategies, one f...
Frank K. H. A. Dehne, Todd Eavis, Susanne E. Hambr...
FOSSACS
2009
Springer
14 years 3 months ago
On Global Model Checking Trees Generated by Higher-Order Recursion Schemes
Higher-order recursion schemes are systems of rewrite rules on typed non-terminal symbols, which can be used to define infinite trees. The Global Modal Mu-Calculus Model Checking...
Christopher Broadbent, C.-H. Luke Ong