111 search results - page 11 / 23 » Using Multiple Memory Access Instructions for Reducing Code ... |
VLSISP
2008
13 years 7 months ago
2008
Many different video processor architectures exist. Its architecture gives a processor strength for a particular application. Hardwired logic yields the best performance/cost, but ...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
Previous object code compression schemes have employed static and semiadaptive compression algorithms to reduce the size of instruction memory in embedded systems. The suggestion ...
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
Code compression is important in embedded systems design since it reduces the code size (memory requirement) and thereby improves overall area, power and performance. Existing res...
ICPP
2003
IEEE
14 years 1 months ago
2003
IEEE
Automatic optimization of address offset assignment for DSP applications, which reduces the number of address arithmetic instructions to meet the tight memory size restrictions an...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...