111 search results - page 12 / 23 » Using Multiple Memory Access Instructions for Reducing Code ... |
SIPS
2007
IEEE
14 years 2 months ago
2007
IEEE
Low Density Parity Check (LDPC) codes are one of the most promising error correction codes that are being adopted by many wireless standards. This paper presents a case study for ...
SBACPAD
2007
IEEE
14 years 2 months ago
2007
IEEE
Code Compression has been used to alleviate the memory requirements as well as to improve performance and/or minimize energy consumption. On the other hand, implementing security ...
IPPS
1996
IEEE
13 years 12 months ago
1996
IEEE
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...
EUROPAR
1999
Springer
14 years 12 hour ago
1999
Springer
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
IAJIT
2010
13 years 6 months ago
2010
: In this paper, new code families are constructed for spectral-amplitude coding optical code division multiple access, called random diagonal code for spectral amplitude coding op...