111 search results - page 6 / 23 » Using Multiple Memory Access Instructions for Reducing Code ... |
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
This paper deals with address assignment in code generation for digital signal processors (DSPs) with SIMD (single instruction multiple data) memory accesses. In these processors ...
MASCOTS
1994
13 years 9 months ago
1994
We investigate the feasibility of using instruction compression at some level in a multi-level memory hierarchy to increase memory system performance. Compression e ectively incre...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
Pointer bugs associated with dynamically-allocated objects resulting in out-of-bounds memory access are an important class of software bugs. Because such bugs cannot be detected e...
VLDB
2004
ACM
14 years 1 months ago
2004
ACM
Online transaction processing (OLTP) is a multibillion dollar industry with high-end database servers employing state-of-the-art processors to maximize performance. Unfortunately,...
IEEEPACT
2002
IEEE
14 years 19 days ago
2002
IEEE
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...