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» Using Queue Time Predictions for Processor Allocation
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SIAMSC
2010
140views more  SIAMSC 2010»
13 years 6 months ago
Parallel High-Order Integrators
In this work we discuss a class of defect correction methods which is easily adapted to create parallel time integrators for multi-core architectures and is ideally suited for deve...
Andrew J. Christlieb, Colin B. Macdonald, Benjamin...
CISIS
2009
IEEE
14 years 2 months ago
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
Francisco Gilabert Villamón, Daniele Ludovi...
ICDCSW
2009
IEEE
14 years 2 months ago
A Dynamic Battery Model for Co-design in Cyber-Physical Systems
We introduce a dynamic battery model that describes the variations of the capacity of a battery under time varying discharge current. This model supports a co-design approach for ...
Fumin Zhang, Zhenwu Shi, Wayne Wolf
ASPDAC
2005
ACM
133views Hardware» more  ASPDAC 2005»
13 years 9 months ago
A novel O(n) parallel banker's algorithm for System-on-a-Chip
This paper proposes a novel O(n) Parallel Banker’s Algorithm (PBA) with a best-case run-time of O(1), reduced from an ¢¤£¦¥¨§© run-time complexity of the original Ban...
Jaehwan John Lee, Vincent John Mooney III
ICSE
2005
IEEE-ACM
14 years 7 months ago
Predictors of customer perceived software quality
Predicting software quality as perceived by a customer may allow an organization to adjust deployment to meet the quality expectations of its customers, to allocate the appropriat...
Audris Mockus, Ping Zhang, Paul Luo Li