610 search results - page 105 / 122 » Using SAT in QBF |
TABLEAUX
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. Model checking is a technique for verifying that a finite-state concurrent system is correct with respect to its specification. In bounded model checking (BMC), the sys...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper describes an improved approach to Boolean network optimization using internal don’t-cares. The improvements concern the type of don’t-cares computed, their scope, a...
FROCOS
2005
Springer
14 years 1 months ago
2005
Springer
We describe results and status of a sub project of the Verisoft [1] project. While the Verisoft project aims at verification of a complete computer system starting with hardware a...
LATIN
2004
Springer
14 years 1 months ago
2004
Springer
Equality logic with or without uninterpreted functions is used for proving the equivalence or refinement between systems (hardware verification, compiler’s translation, etc). C...
ICAT
2003
IEEE
14 years 1 months ago
2003
IEEE
Virtual reality is often used to simulate environments in which the direction of up is not aligned with the normal direction of gravity or the body. How effective are these enviro...