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» Using SAT-based techniques in power estimation
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ISLPED
1997
ACM
130views Hardware» more  ISLPED 1997»
13 years 11 months ago
K2: an estimator for peak sustainable power of VLSI circuits
New measures of peak power in the context of sequential circuits are proposed. This paper presents an automatic procedure to obtain very good lower bounds on these measures as wel...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
ICCD
2004
IEEE
105views Hardware» more  ICCD 2004»
14 years 4 months ago
Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation
In this paper we discuss the application of circuit-based logical reasoning to simplify optimization problems expressed as integer linear programs (ILP) over circuit states. We de...
Donald Chai, Andreas Kuehlmann
ISCAS
2002
IEEE
125views Hardware» more  ISCAS 2002»
14 years 23 days ago
Switching activity estimation of finite state machines for low power synthesis
A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...
Mikael Kerttu, Per Lindgren, Mitchell A. Thornton,...
ISSS
2000
IEEE
127views Hardware» more  ISSS 2000»
14 years 6 days ago
Lower Bound Estimation for Low Power High-Level Synthesis
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Sta...
ISCAS
2008
IEEE
115views Hardware» more  ISCAS 2008»
14 years 2 months ago
FSMD partitioning for low power using simulated annealing
— It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partiti...
Nainesh Agarwal, Nikitas J. Dimopoulos