453 search results - page 27 / 91 » Using Symbolic Simulation for Bounded Property Checking |
ICSE
2010
IEEE-ACM
13 years 9 months ago
2010
IEEE-ACM
The transition from single-core to multi-core processors has made multi-threaded software an important subject over the last years in computer-aided verification. Model checkers ...
MEMOCODE
2003
IEEE
14 years 24 days ago
2003
IEEE
— Modern SAT solvers have proved highly successful in finding counterexamples to temporal properties of systems, using a method known as ”bounded model checking”. It is natu...
ENTCS
2007
13 years 7 months ago
2007
We describe techniques for diagnosing errors in formal equivalence checking of RTL and transistor level models of high performance microprocessors at Freescale Semiconductor Inc. ...
CAV
2001
Springer
13 years 11 months ago
2001
Springer
In this paper we present the application of generalized retiming for temporal property checking. Retiming is a structural transformation that relocates registers in a circuit-based...
CSFW
2009
IEEE
14 years 2 months ago
2009
IEEE
We present a formal model for modeling and reasoning about security protocols. Our model extends standard, inductive, trace-based, symbolic approaches with a formalization of phys...