Error Diagnosis in Equivalence Checking of High Performance Microprocessors

We describe techniques for diagnosing errors in formal equivalence checking of RTL and transistor level models of high performance microprocessors at Freescale Semiconductor Inc. We use Symbolic Trajectory based Evalaution (STE) for combinational equivalence checking. STE accurately captures transistor level behaviors. We use simulation based error diagnosis techniques and present a seamless integration of them in our current verification environments.

• Type: Journal
• Year: 2007
• Where: ENTCS
• Authors: Alper Sen
• Keywords: ENTCS 2007, Transistor Level, Transistor Level Behaviors, Transistor Level Models