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» Using Transformations and Verification in Circuit Design
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127
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EMSOFT
2008
Springer
15 years 5 months ago
Automatically transforming and relating Uppaal models of embedded systems
Relations between models are important for effective automatic validation, for comparing implementations with specifications, and for increased understanding of embedded systems d...
Timothy Bourke, Arcot Sowmya
ICCAD
1995
IEEE
113views Hardware» more  ICCAD 1995»
15 years 7 months ago
Logic decomposition during technology mapping
—A problem in technology mapping is that the quality of the final implementation depends significantly on the initially provided circuit structure. This problem is critical, es...
Eric Lehman, Yosinori Watanabe, Joel Grodstein, He...
236
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POPL
2008
ACM
16 years 4 months ago
Formal verification of translation validators: a case study on instruction scheduling optimizations
Translation validation consists of transforming a program and a posteriori validating it in order to detect a modification of its semantics. This approach can be used in a verifie...
Jean-Baptiste Tristan, Xavier Leroy
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
15 years 10 months ago
Efficient testbench code synthesis for a hardware emulator system
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
Ioannis Mavroidis, Ioannis Papaefstathiou
CASES
2010
ACM
15 years 21 days ago
Optimizing energy to minimize errors in dataflow graphs using approximate adders
Approximate arithmetic is a promising, new approach to lowenergy designs while tackling reliability issues. We present a method to optimally distribute a given energy budget among...
Zvi M. Kedem, Vincent John Mooney, Kirthi Krishna ...