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» Using a SAT solver to generate checking sequences
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TABLEAUX
2007
Springer
14 years 1 months ago
Bounded Model Checking with Description Logic Reasoning
Abstract. Model checking is a technique for verifying that a finite-state concurrent system is correct with respect to its specification. In bounded model checking (BMC), the sys...
Shoham Ben-David, Richard J. Trefler, Grant E. Wed...
LION
2010
Springer
190views Optimization» more  LION 2010»
13 years 11 months ago
Algorithm Selection as a Bandit Problem with Unbounded Losses
Abstract. Algorithm selection is typically based on models of algorithm performance learned during a separate offline training sequence, which can be prohibitively expensive. In r...
Matteo Gagliolo, Jürgen Schmidhuber
ATVA
2007
Springer
108views Hardware» more  ATVA 2007»
14 years 1 months ago
A New Approach to Bounded Model Checking for Branching Time Logics
Abstract. Bounded model checking (BMC) is a technique for overcoming the state explosion problem which has gained wide industrial acceptance. Bounded model checking is typically ap...
Rotem Oshman, Orna Grumberg
TACAS
2010
Springer
255views Algorithms» more  TACAS 2010»
13 years 5 months ago
Satisfiability Modulo the Theory of Costs: Foundations and Applications
Abstract. We extend the setting of Satisfiability Modulo Theories (SMT) by introducing a theory of costs C, where it is possible to model and reason about resource consumption and ...
Alessandro Cimatti, Anders Franzén, Alberto...
DAC
2003
ACM
14 years 8 months ago
Behavioral consistency of C and verilog programs using bounded model checking
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
Edmund M. Clarke, Daniel Kroening, Karen Yorav