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» Using a Swap Instruction to Coalesce Loads and Stores
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LCPC
2004
Springer
14 years 22 days ago
Speculative Subword Register Allocation in Embedded Processors
Abstract. Multimedia and network processing applications make extensive use of subword data. Since registers are capable of holding a full data word, when a subword variable is ass...
Bengu Li, Youtao Zhang, Rajiv Gupta
ASAP
2007
IEEE
219views Hardware» more  ASAP 2007»
14 years 1 months ago
SIMD Vectorization of Histogram Functions
Existing SIMD extensions cannot efficiently vectorize the histogram function due to memory collisions. We propose two techniques to avoid this problem. In the first, a hierarchi...
Asadollah Shahbahrami, Ben H. H. Juurlink, Stamati...
MICRO
1997
IEEE
86views Hardware» more  MICRO 1997»
13 years 11 months ago
Streamlining Inter-Operation Memory Communication via Data Dependence Prediction
We revisit memory hierarchy design viewing memory as an inter-operation communication agent. This perspective leads to the development of novel methods of performing inter-operati...
Andreas Moshovos, Gurindar S. Sohi
POPL
2009
ACM
14 years 8 months ago
Feedback-directed barrier optimization in a strongly isolated STM
Speed improvements in today's processors have largely been delivered in the form of multiple cores, increasing the importance of ions that ease parallel programming. Software...
Nathan Grasso Bronson, Christos Kozyrakis, Kunle O...
CF
2010
ACM
14 years 14 days ago
EXACT: explicit dynamic-branch prediction with active updates
Branches that depend directly or indirectly on load instructions are a leading cause of mispredictions by state-of-the-art branch predictors. For a branch of this type, there is a...
Muawya Al-Otoom, Elliott Forbes, Eric Rotenberg