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GECCO
2009
Springer
192views Optimization» more  GECCO 2009»
13 years 5 months ago
Improving SMT performance: an application of genetic algorithms to configure resizable caches
Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallel...
Josefa Díaz, José Ignacio Hidalgo, F...
IWMM
2011
Springer
217views Hardware» more  IWMM 2011»
12 years 10 months ago
On the theory and potential of LRU-MRU collaborative cache management
The goal of cache management is to maximize data reuse. Collaborative caching provides an interface for software to communicate access information to hardware. In theory, it can o...
Xiaoming Gu, Chen Ding
TC
1998
13 years 7 months ago
Optimizing the Instruction Cache Performance of the Operating System
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
Josep Torrellas, Chun Xia, Russell L. Daigle
ICASSP
2008
IEEE
14 years 2 months ago
A weighted subspace approach for improving bagging performance
Bagging is an ensemble method that uses random resampling of a dataset to construct models. In classification scenarios, the random resampling procedure in bagging induces some c...
Qu-Tang Cai, Chun-Yi Peng, Chang-Shui Zhang
DAC
2010
ACM
13 years 7 months ago
Instruction cache locking using temporal reuse profile
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
Yun Liang, Tulika Mitra