189 search results - page 35 / 38 » Using constraint logic programming in memory synthesis for g... |
EMSOFT
2007
Springer
14 years 1 months ago
2007
Springer
This paper describes techniques to estimate the worst case execution time of executable code on architectures with data caches. The underlying mechanism is Abstract Interpretation...
CF
2009
ACM
14 years 2 months ago
2009
ACM
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...
CCS
2003
ACM
14 years 21 days ago
2003
ACM
To achieve security in wireless sensor networks, it is important to be able to encrypt and authenticate messages sent among sensor nodes. Keys for encryption and authentication pu...