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» Using general-purpose programming languages for FPGA design
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118
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ASPLOS
2006
ACM
15 years 8 months ago
Introspective 3D chips
While the number of transistors on a chip increases exponentially over time, the productivity that can be realized from these systems has not kept pace. To deal with the complexit...
Shashidhar Mysore, Banit Agrawal, Navin Srivastava...
123
Voted
ASPLOS
1994
ACM
15 years 6 months ago
Reactive Synchronization Algorithms for Multiprocessors
Synchronization algorithms that are efficient across a wide range of applications and operating conditions are hard to design because their performance depends on unpredictable ru...
Beng-Hong Lim, Anant Agarwal
228
Voted
ASPLOS
2009
ACM
16 years 3 months ago
Mixed-mode multicore reliability
Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly ...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...
ASPLOS
2008
ACM
15 years 4 months ago
Accelerating two-dimensional page walks for virtualized systems
Nested paging is a hardware solution for alleviating the software memory management overhead imposed by system virtualization. Nested paging complements existing page walk hardwar...
Ravi Bhargava, Ben Serebrin, Francesco Spadini, Sr...
120
Voted
ASPLOS
2008
ACM
15 years 4 months ago
No "power" struggles: coordinated multi-level power management for the data center
Power delivery, electricity consumption, and heat management are becoming key challenges in data center environments. Several past solutions have individually evaluated different ...
Ramya Raghavendra, Parthasarathy Ranganathan, Vani...