280 search results - page 20 / 56 » Using generative design patterns to generate parallel code f... |
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or specul...
EUROPAR
2006
Springer
13 years 11 months ago
2006
Springer
Multi-resolution validation of hierarchical performance models of scientific applications is critical primarily for two reasons. First, the step-by-step validation determines the c...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
EUROPAR
2000
Springer
13 years 11 months ago
2000
Springer
Abstract. Current approaches to parallel I/O demand extensive user effort to obtain acceptable performance. This is in part due to difficulties in understanding the characteristics...
ISPAN
2009
IEEE
14 years 2 months ago
2009
IEEE
—In this paper, we present a design architecture of implementing a ”Vector Bank” into video encoder system, namely, an H.264 encoder, in order to detect and analyze the movin...