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WSC
2004
13 years 8 months ago
Towards Adaptive Caching for Parallel and Discrete Event Simulation
We investigate factors that impact the effectiveness of caching to speed up discrete event simulation. Walsh and Sirer have shown that a variant of function caching (staged simula...
Abhishek Chugh, Maria Hybinette
ISQED
2008
IEEE
186views Hardware» more  ISQED 2008»
14 years 1 months ago
Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...
Foad Dabiri, Navid Amini, Mahsan Rofouei, Majid Sa...
ICPR
2008
IEEE
14 years 8 months ago
Rapid signer adaptation for continuous sign language recognition using a combined approach of eigenvoices, MLLR, and MAP
Current sign language recognition systems are still designed for signer-dependent operation only and thus suffer from the problem of interpersonal variability in production. Appli...
Christoph Blömer, Karl-Friedrich Kraiss, Ulri...
ISCA
1997
IEEE
103views Hardware» more  ISCA 1997»
13 years 11 months ago
Designing High Bandwidth On-Chip Caches
In this paper we evaluate the performance of high bandwidth caches that employ multiple ports, multiple cycle hit times, on-chip DRAM, and a line buffer to find the organization t...
Kenneth M. Wilson, Kunle Olukotun
SIGARCH
2008
96views more  SIGARCH 2008»
13 years 6 months ago
Towards hybrid last level caches for chip-multiprocessors
As CMP platforms are widely adopted, more and more cores are integrated on to the die. To reduce the off-chip memory access, the last level cache is usually organized as a distribu...
Li Zhao, Ravi Iyer, Mike Upton, Don Newell