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VLSID
2002
IEEE
125views VLSI» more  VLSID 2002»
16 years 3 months ago
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
Francisco Barat, Murali Jayapala, Pieter Op de Bee...
HPCC
2009
Springer
15 years 1 months ago
Graph-Based Task Replication for Workflow Applications
Abstract--The Grid is an heterogeneous and dynamic environment which enables distributed computation. This makes it a technology prone to failures. Some related work uses replicati...
Raúl Sirvent, Rosa M. Badia, Jesús L...
176
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SIGOPS
2010
179views more  SIGOPS 2010»
14 years 10 months ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...
CP
2003
Springer
15 years 8 months ago
Open Constraint Optimization
Constraint satisfaction has been applied with great success in closed-world scenarios, where all options and constraints are known from the beginning and fixed. With the internet,...
Boi Faltings, Santiago Macho-Gonzalez
150
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ISSS
2000
IEEE
127views Hardware» more  ISSS 2000»
15 years 7 months ago
Lower Bound Estimation for Low Power High-Level Synthesis
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Sta...