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STTT
2010
115views more  STTT 2010»
13 years 5 months ago
Scalable shared memory LTL model checking
Recent development in computer hardware has brought more wide-spread emergence of shared memory, multi-core systems. These architectures offer opportunities to speed up various ta...
Jiri Barnat, Lubos Brim, Petr Rockai
ICS
2004
Tsinghua U.
14 years 3 days ago
Applications of storage mapping optimization to register promotion
Storage mapping optimization is a flexible approach to folding array dimensions in numerical codes. It is designed to reduce the memory footprint after a wide spectrum of loop tr...
Patrick Carribault, Albert Cohen
ASPDAC
2006
ACM
141views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Depth-driven verification of simultaneous interfaces
The verification of modern computing systems has grown to dominate the cost of system design, often with limited success as designs continue to be released with latent bugs. This t...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
ICPP
2002
IEEE
13 years 11 months ago
Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...
Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
HIPC
2007
Springer
14 years 27 days ago
Channel Adaptive Real-Time MAC Protocols for a Two-Level Heterogeneous Wireless Network
Abstract. Wireless technology is becoming an attractive mode of communication for real-time applications in typical settings such as in an industrial setup because of the tremendou...
Kavitha Balasubramanian, G. Sudha Anil Kumar, G. M...