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» Using the Compiler to Improve Cache Replacement Decisions
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NOCS
2007
IEEE
14 years 29 days ago
Implementation and Evaluation of a Dynamically Routed Processor Operand Network
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...
Paul Gratz, Karthikeyan Sankaralingam, Heather Han...
CCGRID
2007
IEEE
14 years 1 months ago
Study of Different Replica Placement and Maintenance Strategies in Data Grid
Data replication is an excellent technique to move and cache data close to users. By replication, data access performance can be improved dramatically. One of the challenges in da...
Rashedur M. Rahman, Ken Barker, Reda Alhajj
WIA
2004
Springer
14 years 15 hour ago
A BDD-Like Implementation of an Automata Package
In this paper we propose a new data structure, called shared automata, for representing deterministic finite automata (DFA). Shared automata admit a strong canonical form for DFA ...
Jean-Michel Couvreur
FMSD
2007
110views more  FMSD 2007»
13 years 6 months ago
Exploiting interleaving semantics in symbolic state-space generation
Symbolic techniques based on Binary Decision Diagrams (BDDs) are widely employed for reasoning about temporal properties of hardware circuits and synchronous controllers. However, ...
Gianfranco Ciardo, Gerald Lüttgen, Andrew S. ...
CODES
2004
IEEE
13 years 10 months ago
Optimizing the memory bandwidth with loop fusion
The memory bandwidth largely determines the performance and energy cost of embedded systems. At the compiler level, several techniques improve the memory bandwidth at the scope of...
Paul Marchal, José Ignacio Gómez, Fr...