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ICASSP
2008
IEEE
15 years 11 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
MMSP
2008
IEEE
147views Multimedia» more  MMSP 2008»
15 years 11 months ago
Bit allocation for spatial scalability in H.264/SVC
Abstract—We propose a model-based spatial layer bit allocation algorithm for H.264/SVC in this work. The spatial scalability of H.264/SVC is achieved by a multi-layer approach, w...
Jiaying Liu, Yongjin Cho, Zongming Guo, C. C. Jay ...
P2P
2008
IEEE
15 years 11 months ago
Faster Content Access in KAD
Many different Distributed Hash Tables (DHTs) have been designed, but only few have been successfully deployed. The implementation of a DHT needs to deal with practical aspects (e...
Moritz Steiner, Damiano Carra, Ernst W. Biersack
VTC
2007
IEEE
115views Communications» more  VTC 2007»
15 years 10 months ago
The DYMO Routing Protocol in VANET Scenarios
—Coupling Vehicular Ad Hoc Networks (VANETs) with wired networks such as the Internet via access points creates a difficult mix of highly mobile nodes and a static infrastructur...
Christoph Sommer, Falko Dressler
143
Voted
IEEECIT
2006
IEEE
15 years 10 months ago
Design and Implementation of Distributed Task Sequencing on GridRPC
In the framework of GridRPC, a new function that allows direct data transfer between RPC servers is implemented for efficient execution of a Task Sequencing job in a grid environ...
Yusuke Tanimura, Hidemoto Nakada, Yoshio Tanaka, S...