Sciweavers

367 search results - page 57 / 74
» Utility-aware Resource Allocation in an Event Processing Sys...
Sort
View
HPCC
2009
Springer
14 years 1 months ago
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures
—The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the ...
Magnus Jahre, Marius Grannæs, Lasse Natvig
ICASSP
2009
IEEE
14 years 13 days ago
What happens when cognitive terminals compete for a relaying node?
We introduce a new channel, which consists of an interference channel (IC) in parallel with an interference relay channel (IRC), to analyze the interaction between two selfish and...
Elena Veronica Belmega, Brice Djeumou, Samson Lasa...
APIN
2006
90views more  APIN 2006»
13 years 8 months ago
AgentTeamwork: Coordinating grid-computing jobs with mobile agents
AgentTeamwork is a grid-computing middleware system that dispatches a collection of mobile agents to coordinate a user job over remote computing nodes in a decentralized manner. I...
Munehiro Fukuda, Koichi Kashiwagi, Shin-ya Kobayas...
ICCCN
2007
IEEE
14 years 2 months ago
Lagniappe: Multi-* Programming Made Simple
—The emergence of multi-processor, multi-threaded architectures (referred to as multi- architectures) facilitates the design of high-throughput request processing systems (e.g., ...
Taylor L. Riché, R. Greg Lavender, Harrick ...
IPPS
2007
IEEE
14 years 2 months ago
Rethinking Automated Synthesis of MPSoC Architectures
Emerging heterogeneous multiprocessors will have custom memory and bus architectures that must balance resource sharing and system partitioning to meet cost constraints. We propos...
Brett H. Meyer, Donald E. Thomas