46 search results - page 6 / 10 » VERILAT: verification using logic augmentation and transform... |
POPL
2005
ACM
14 years 7 months ago
2005
ACM
on Predicate Abstraction and Fair Termination Andreas Podelski Andrey Rybalchenko Max-Planck-Institut f?ur Informatik Saarbr?ucken, Germany Predicate abstraction is the basis of m...
AUSDM
2008
Springer
13 years 9 months ago
2008
Springer
Term signal is an existing text representation that depicts a term as a vector of frequencies of occurrences in a number of user-defined partitions of a document. Although term si...
CODES
2008
IEEE
13 years 9 months ago
2008
IEEE
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
DFG
2004
Springer
13 years 11 months ago
2004
Springer
This paper presents the real-time model checker RAVEN and related theoretical background. RAVEN augments the efficiency of traditional symbolic model checking with possibilities to...
JUCS
2002
13 years 7 months ago
2002
: This paper presents a framework for representing formal semantics of a subset of the Unified Modeling Language (UML) notation in a higher-order logic, more specifically semantics...