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» VLSI Circuit Synthesis Using a Parallel Genetic Algorithm
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CEC
2005
IEEE
14 years 1 months ago
Dynamic power minimization during combinational circuit testing as a traveling salesman problem
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
Artem Sokolov, Alodeep Sanyal, L. Darrell Whitley,...
PPSN
2004
Springer
14 years 27 days ago
Evolving Genetic Regulatory Networks for Hardware Fault Tolerance
We present a new approach that is able to produce an increased fault tolerance in bio-inspired electronic circuits. To this end, we designed hardwarefriendly genetic regulatory net...
Arne Koopman, Daniel Roggen
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
14 years 25 days ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach
IPPS
1997
IEEE
13 years 11 months ago
Parallel Simulated Annealing: An Adaptive Approach
This paper analyses alternatives for the parallelization of the Simulated Annealing algorithm when applied to the placement of modules in a VLSI circuit considering the use of PVM...
Jonas Knopman, Júlio S. Aude
GECCO
2005
Springer
196views Optimization» more  GECCO 2005»
14 years 1 months ago
Providing information from the environment for growing electronic circuits through polymorphic gates
This paper deals with the evolutionary design of programs (constructors) that are able to create (n+2)-input circuits from n-input circuits. The growing circuits are composed of p...
Michal Bidlo, Lukás Sekanina