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» Validating High-Level Synthesis
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ISTA
2008
14 years 11 days ago
From Human Knowledge to Process Models
This contribution suggests a novel approach for a systematic generation of a process model in an informal environment. It is based on the claim that the knowledge about the process...
Jörg Desel
VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
14 years 11 months ago
Variable Resizing for Area Improvement in Behavioral Synthesis
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...
R. Gopalakrishnan, Rajat Moona
EUROMICRO
2006
IEEE
14 years 5 months ago
A Modeling Paradigm for Integrated Modular Avionics Design
This paper presents the modeling paradigm for Integrated Modular Avionics Design MIMAD V0, which is an extensible component-oriented framework that enables high level models of sy...
Abdoulaye Gamatié, Christian Brunette, Roma...
RSP
2005
IEEE
155views Control Systems» more  RSP 2005»
14 years 4 months ago
Optimization Techniques for ADL-Driven RTL Processor Synthesis
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
Oliver Schliebusch, Anupam Chattopadhyay, Ernst Ma...
RE
1997
Springer
14 years 3 months ago
Requirements Models in Context
The field of requirements engineering emerges out of tradition of research and engineering practice that stresses rtance of generalizations and abstractions. abstraction is essent...
Colin Potts