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» Validating High-Level Synthesis
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DAC
2009
ACM
14 years 3 months ago
Non-cycle-accurate sequential equivalence checking
We present a novel technique for Sequential Equivalence Checking (SEC) between non-cycle-accurate designs. The problem is routinely encountered in verifying the correctness of a s...
Pankaj Chauhan, Deepak Goyal, Gagan Hasteer, Anmol...
NIME
2001
Springer
136views Music» more  NIME 2001»
14 years 3 months ago
The MATRIX: A Novel Controller for Musical Expression
The MATRIX (Multipurpose Array of Tactile Rods for Interactive eXpression) is a new musical interface for amateurs and professionals alike. It gives users a 3dimensional tangible ...
Dan Overholt
ASPDAC
2008
ACM
88views Hardware» more  ASPDAC 2008»
14 years 29 days ago
REWIRED - Register Write Inhibition by Resource Dedication
We propose REWIRED (REgister Write Inhibition by REsource Dedication), a technique for reducing power during high level synthesis (HLS) by selectively inhibiting the storage of fun...
Pushkar Tripathi, Rohan Jain, Srikanth Kurra, Pree...
ICCAD
2003
IEEE
124views Hardware» more  ICCAD 2003»
14 years 7 months ago
Gradual Relaxation Techniques with Applications to Behavioral Synthesis
Heuristics are widely used for solving computational intractable synthesis problems. However, until now, there has been limited effort to systematically develop heuristics that ca...
Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason ...
APN
2010
Springer
14 years 3 months ago
AlPiNA: A Symbolic Model Checker
AlPiNA is a symbolic model checker for High Level Petri nets. It is comprised of two independent modules: a GUI plugin for Eclipse and an underlying model checking engine. AlPiNAâ€...
Didier Buchs, Steve Hostettler, Alexis Marechal, M...