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» Validating High-Level Synthesis
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MST
2006
120views more  MST 2006»
13 years 11 months ago
Exploiting Regularities for Boolean Function Synthesis
The "regularity" of a Boolean function can be exploited for decreasing its minimization time. It has already been shown that the notion of autosymmetry is a valid measure...
Anna Bernasconi, Valentina Ciriani, Fabrizio Lucci...
VR
2010
IEEE
135views Virtual Reality» more  VR 2010»
13 years 9 months ago
Sound synthesis and evaluation of interactive footsteps for virtual reality applications
A system to synthesize in real-time the sound of footsteps on different materials is presented. The system is based on microphones which allow the user to interact with his own fo...
Rolf Nordahl, Stefania Serafin, Luca Turchet
ICNC
2009
Springer
14 years 5 months ago
Reducing Boarding Time: Synthesis of Improved Genetic Algorithms
—With the aim to minimize boarding time and devise procedures for boarding strategies, this paper develop the synthesis of Improved Genetic Algorithms and simulation. This paper ...
Kang Wang
IRI
2008
IEEE
14 years 5 months ago
Modeling and synthesis of service composition using tree automata
— We revisit the problem of synthesis of service composition in the context of service oriented architecture from a tree automata perspective. Comparing to existing finite state...
Ken Q. Pu, Ying Zhu
DATE
2006
IEEE
86views Hardware» more  DATE 2006»
14 years 5 months ago
Synthesis of system verilog assertions
In recent years, Assertion-Based Verification is being widely accepted as a key technology in the pre-silicon validation of system-on-chip(SOC) designs. The System Verilog langua...
Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P....