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» Validating High-Level Synthesis
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ICASSP
2011
IEEE
13 years 2 months ago
Further analysis of latent affective mapping for naturally expressive speech synthesis
An essential step in the generation of expressive speech synthesis is the automatic detection and classification of emotions most likely to be present in textual input. At last I...
Jerome R. Bellegarda
POPL
2010
ACM
14 years 5 months ago
Abstraction-guided synthesis of synchronization
ion-Guided Synthesis of Synchronization Martin Vechev IBM Research Eran Yahav IBM Research Greta Yorsh IBM Research We present a novel framework for automatic inference of effici...
Martin T. Vechev, Eran Yahav, Greta Yorsh
DATE
2007
IEEE
83views Hardware» more  DATE 2007»
14 years 5 months ago
High-level test synthesis for delay fault testability
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
Sying-Jyan Wang, Tung-Hua Yeh
UML
1998
Springer
14 years 3 months ago
Automating the Synthesis of UML StateChart Diagrams from Multiple Collaboration Diagrams
The use of scenarios has become a popular technique for requirements elicitation and specification building. Since scenarios capture only partial descriptions of system behavior, ...
Ismaïl Khriss, Mohammed Elkoutbi, Rudolf K. K...
ITC
1997
IEEE
80views Hardware» more  ITC 1997»
14 years 3 months ago
Scan Synthesis for One-Hot Signals
Tri-state buses and pass transistor logic are used in many complex applications to achieve high performance and small area. Such circuits often contain logic requiring one-hot sig...
Subhasish Mitra, LaNae J. Avra, Edward J. McCluske...