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» Validating High-Level Synthesis
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ICCAD
2010
IEEE
117views Hardware» more  ICCAD 2010»
13 years 9 months ago
A synthesis flow for digital signal processing with biomolecular reactions
Abstract--We present a methodology for implementing digital signal processing (DSP) operations such as filtering with biomolecular reactions. From a DSP specification, we demonstra...
Hua Jiang, Aleksandra P. Kharam, Marc D. Riedel, K...
HICSS
2009
IEEE
106views Biometrics» more  HICSS 2009»
14 years 5 months ago
IT Capacities Assessment Tool: A Survey of Hospitals in Canada
This study presents an IT assessment tool that aims at capturing the level of IT sophistication in hospitals. In order to develop a measure that reflects IT capacities in hospital...
Mirou Jaana, Guy Paré, Claude Sicotte
FMCAD
2009
Springer
14 years 2 months ago
Industrial strength refinement checking
This paper discusses a methodology used on an industrial hardware development project to validate various cache-coherence protocol components. The idea is to use a high level model...
Jesse D. Bingham, John Erickson, Gaurav Singh, Fle...
AMAST
2006
Springer
14 years 2 months ago
Formal Islands
Abstract. Motivated by the proliferation and usefulness of Domain Specific Languages as well as the demand in enriching well established languages by high level capabilities like p...
Emilie Balland, Claude Kirchner, Pierre-Etienne Mo...
CEC
2010
IEEE
14 years 3 days ago
A novel framework to elucidate core classes in a dataset
In this paper we present an original framework to extract representative groups from a dataset, and we validate it over a novel case study. The framework specifies the application ...
Daniele Soria, Jonathan M. Garibaldi