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» Validating Register Allocation and Spilling
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DAC
1995
ACM
13 years 11 months ago
Code Optimization Techniques for Embedded DSP Microprocessors
—We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventiona...
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Stev...
CC
2003
Springer
114views System Software» more  CC 2003»
14 years 20 days ago
Combined Code Motion and Register Allocation Using the Value State Dependence Graph
We define the Value State Dependence Graph (VSDG). The VSDG is a form of the Value Dependence Graph (VDG) extended by the addition of state dependence edges to model sequentialise...
Neil Johnson, Alan Mycroft
PLDI
2004
ACM
14 years 26 days ago
Balancing register allocation across threads for a multithreaded network processor
+ Modern network processors employ multi-threading to allow concurrency amongst multiple packet processing tasks. We studied the properties of applications running on the network p...
Xiaotong Zhuang, Santosh Pande
IEEEPACT
1998
IEEE
13 years 11 months ago
Optimistic Register Coalescing
Register coalescing is used, as part of register allocation, to reduce the number of register copies. Developing efficient register coalescing heuristics is particularly important ...
Jinpyo Park, Soo-Mook Moon
ASPLOS
1998
ACM
13 years 11 months ago
Compiler-Controlled Memory
Optimizations aimed at reducing the impact of memory operations on execution speed have long concentrated on improving cache performance. These efforts achieve a reasonable level...
Keith D. Cooper, Timothy J. Harvey