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» Variation-aware routing for FPGAs
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FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
14 years 4 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen
FPL
2007
Springer
106views Hardware» more  FPL 2007»
14 years 1 months ago
RAMP Blue: A Message-Passing Manycore System in FPGAs
We are developing a set of reusable design blocks and several prototype systems for emulation of multi-core architectures in FPGAs. RAMP Blue is the first of these prototypes and...
Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg...
ERSA
2004
129views Hardware» more  ERSA 2004»
13 years 9 months ago
A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs
Platform FPGAs incorporate many different components, such as processor core(s), reconfigurable logic, memory, etc., onto a single chip. When an application is synthesized on platf...
Jingzhao Ou, Viktor K. Prasanna
DAC
2005
ACM
14 years 8 months ago
Logic block clustering of large designs for channel-width constrained FPGAs
In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2, 3, 11] aim to red...
Marvin Tom, Guy G. Lemieux
FPL
2005
Springer
98views Hardware» more  FPL 2005»
14 years 1 months ago
A Verilog RTL Synthesis Tool for Heterogeneous FPGAs
Modern heterogeneous FPGAs contain “hard” specificpurpose structures such as blocks of memory and multipliers in addition to the completely flexible “soft” programmable ...
Peter Jamieson, Jonathan Rose