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15 years 7 months ago
Within-die Process Variations: How Accurately can They Be Statistically Modeled?
Within-die process variations arise during integrated circuit (IC) fabrication in the sub-100nm regime. These variations are of paramount concern as they deviate the performance of...
Brendan Hargreaves, Henrik Hult, Sherief Reda
ICDAR
2009
IEEE
13 years 5 months ago
Stochastic Model of Stroke Order Variation
A stochastic model of stroke order variation is proposed and applied to the stroke-order free on-line Kanji character recognition. The proposed model is a hidden Markov model (HMM...
Yoshinori Katayama, Seiichi Uchida, Hiroaki Sakoe
UML
2005
Springer
14 years 1 months ago
Code Generation from UML Models with Semantic Variation Points
UML semantic variation points provide intentional degrees of freedom for the interpretation of the metamodel semantics. The interest of semantic variation points is that UML now b...
Franck Chauvel, Jean-Marc Jézéquel
DAC
2005
ACM
13 years 9 months ago
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach
A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...
Yu Cao, Lawrence T. Clark
GLVLSI
2005
IEEE
205views VLSI» more  GLVLSI 2005»
14 years 1 months ago
Optimization objectives and models of variation for statistical gate sizing
This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exc...
Matthew R. Guthaus, Natesan Venkateswaran, Vladimi...