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» Verification Environment for a SCMP Architecture
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JUCS
2010
130views more  JUCS 2010»
13 years 2 months ago
Toward an Integrated Tool Environment for Static Analysis of UML Class and Sequence Models
: There is a need for more rigorous analysis techniques that developers can use for verifying the critical properties in UML models. The UML-based Specification Environment (USE) t...
Wuliang Sun, Eunjee Song, Paul C. Grabow, Devon M....
DAC
2007
ACM
13 years 11 months ago
Verification Methodologies in a TLM-to-RTL Design Flow
SoC based system developments commonly employ ESL design ogies and utilize multiple levels of abstract models to provide feasibility study models for architects and development pl...
Atsushi Kasuya, Tesh Tesfaye
ENTCS
2006
90views more  ENTCS 2006»
13 years 7 months ago
Runtime Verification for High-Confidence Systems: A Monte Carlo Approach
We present a new approach to runtime verification that utilizes classical statistical techniques such as Monte Carlo simulation, hypothesis testing, and confidence interval estima...
Sean Callanan, Radu Grosu, Abhishek Rai, Scott A. ...
IJCAI
1993
13 years 8 months ago
A Model-Theoretic Approach to the Verification of Situated Reasoning Systems
agent-oriented system. We show the complexity to be linear time for one of these logics and polynomial time for another, thus providing encouraging results with respect to the prac...
Anand S. Rao, Michael P. Georgeff
RCC
2002
104views more  RCC 2002»
13 years 7 months ago
Architectural Specification, Exploration and Simulation Through Rewriting-Logic
In recent years Arvind's Group at MIT has shown the usefulness of term rewriting theory for the specification of processor architectures. In their approach processors specifi...
Mauricio Ayala-Rincón, Reiner W. Hartenstei...