Sciweavers

114 search results - page 7 / 23
» Verification by Simulation Comparison using Interface Synthe...
Sort
View
DAC
2009
ACM
14 years 9 months ago
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
VR
2003
IEEE
126views Virtual Reality» more  VR 2003»
14 years 1 months ago
A Taxonomy and Comparison of Haptic Actions for Disassembly Tasks
The usefulness of modern day haptics equipment for virtual simulations of actual maintenance actions is examined. In an effort to categorize which areas haptic simulations may be ...
Aaron Bloomfield, Yu Deng, Jeff Wampler, Pascale R...
ICSE
2008
IEEE-ACM
14 years 8 months ago
Temporal dependency based checkpoint selection for dynamic verification of fixed-time constraints in grid workflow systems
In grid workflow systems, temporal correctness is critical to assure the timely completion of grid workflow execution. To monitor and control the temporal correctness, fixed-time ...
Jinjun Chen, Yun Yang
TCAD
2002
121views more  TCAD 2002»
13 years 7 months ago
Robust Boolean reasoning for equivalence checking and functional property verification
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, ...
FMOODS
2006
13 years 9 months ago
Bounded Analysis and Decomposition for Behavioural Descriptions of Components
Abstract. Explicit behavioural interfaces are now accepted as a mandatory feature of components to address architectural analysis. Behavioural interface description languages shoul...
Pascal Poizat, Jean-Claude Royer, Gwen Salaün