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» Verification of Equivalent-Results Methods
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JUCS
2002
146views more  JUCS 2002»
13 years 9 months ago
A Framework for Semantics of UML Sequence Diagrams in PVS
: This paper presents a framework for representing formal semantics of a subset of the Unified Modeling Language (UML) notation in a higher-order logic, more specifically semantics...
Demissie B. Aredo
TSE
2002
94views more  TSE 2002»
13 years 9 months ago
Improving the Precision of INCA by Eliminating Solutions with Spurious Cycles
The Inequality Necessary Condition Analyzer (INCA) is a finite-state verification tool that has been able to check properties of some very large concurrent systems. INCA checks a p...
Stephen F. Siegel, George S. Avrunin
ICCAD
2010
IEEE
140views Hardware» more  ICCAD 2010»
13 years 8 months ago
Reduction of interpolants for logic synthesis
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...
John D. Backes, Marc D. Riedel
FLAIRS
2009
13 years 7 months ago
Constraint-based Approach to Discovery of Inter Module Dependencies in Modular Bayesian Networks
This paper introduces an information theoretic approach to verification of modular causal probabilistic models. We assume systems which are gradually extended by adding new functi...
Patrick de Oude, Gregor Pavlin
GI
2009
Springer
13 years 7 months ago
Project Planning Support by Model Checking
Abstract: Today's trend in software and system engineering is to utilize more specialized models. This model-based development approach makes a single engineering task more ea...
Björn Axenath, Oliver Sudmann