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» Verification of Equivalent-Results Methods
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IEICET
2006
114views more  IEICET 2006»
13 years 8 months ago
Synchronization Verification in System-Level Design with ILP Solvers
Concurrency is one of the most important issues in system-level design. Interleaving among parallel processes can cause an extremely large number of different behaviors, making de...
Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro ...
GLVLSI
2009
IEEE
323views VLSI» more  GLVLSI 2009»
13 years 6 months ago
MYGEN: automata-based on-line test generator for assertion-based verification
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...
Yann Oddos, Katell Morin-Allory, Dominique Borrion...
JDCTA
2010
144views more  JDCTA 2010»
13 years 3 months ago
Research on SVDD Applied in Speaker Verification
In tradition probability statistics model, speaker verification threshold is instability in different test situations. A novel speaker verification method based on Support Vector ...
Yuhuan Zhou, Xiongwei Zhang, Jinming Wang, Yong Go...
FMCAD
2007
Springer
14 years 19 days ago
Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs
Abstract--Analog and mixed signal (AMS) designs are important integrated circuits that are usually needed at the interface between the electronic system and the real world. Recentl...
Mohamed H. Zaki, Ghiath Al Sammane, Sofiène...
FORMATS
2009
Springer
14 years 19 days ago
Stochastic Games for Verification of Probabilistic Timed Automata
Probabilistic timed automata (PTAs) are used for formal modelling and verification of systems with probabilistic, nondeterministic and real-time behaviour. For non-probabilistic ti...
Marta Z. Kwiatkowska, Gethin Norman, David Parker