37 search results - page 4 / 8 » Verification of Floating-Point Adders |
CADE
2010
Springer
13 years 8 months ago
2010
Springer
Abstract. In the context of deductive program verification, supporting floatingpoint computations is tricky. We propose an expressive language to formally specify behavioral proper...
TC
2010
13 years 6 months ago
2010
—Due to the widespread use and inherent complexity of floating-point addition, much effort has been devoted to its speedup via algorithmic and circuit techniques. We propose a ne...
CHARME
2001
Springer
13 years 11 months ago
2001
Springer
We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The ...
ARITH
1997
IEEE
13 years 11 months ago
1997
IEEE
Engineering design methodology recommends designing a system as follows: Start with an unambiguous speci cation, partition the system into blocks, specify the functionality of eac...
FPL
2006
Springer
13 years 11 months ago
2006
Springer
FPGAs have reached densities that can implement floatingpoint applications, but floating-point operations still require a large amount of FPGA resources. One major component of IE...