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» Verification of System Level Model Transformations
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101
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ICFEM
2007
Springer
15 years 8 months ago
Machine-Assisted Proof Support for Validation Beyond Simulink
Simulink is popular in industry for modeling and simulating embedded systems. It is deficient to handle requirements of high-level assurance and timing analysis. Previously, we sh...
Chunqing Chen, Jin Song Dong, Jun Sun 0001
129
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FASE
2007
Springer
15 years 8 months ago
Scenario-Driven Dynamic Analysis of Distributed Architectures
Abstract. Software architecture constitutes a promising approach to the development of large-scale distributed systems, but architecture description languages (ADLs) and their asso...
George Edwards, Sam Malek, Nenad Medvidovic
DAC
1999
ACM
15 years 6 months ago
Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration
This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications. We implemented this approach in the VASE behavioral-synthesis tool. ...
Alex Doboli, Adrián Núñez-Ald...
FDL
2008
IEEE
15 years 4 months ago
RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow
In this paper, we propose the design methodology for communication channel templates from formal specification to RTL description. In this flow, design and verification start from...
Jinhyun Cho, Soonwoo Choi, Soo Chae
ACL
2012
13 years 5 months ago
Lemmatisation as a Tagging Task
We present a novel approach to the task of word lemmatisation. We formalise lemmatisation as a category tagging task, by describing how a word-to-lemma transformation rule can be ...
Andrea Gesmundo, Tanja Samardzic