196 search results - page 16 / 40 » Verification of timing Properties of VHDL |
FDL
2004
IEEE
13 years 11 months ago
2004
IEEE
gn process of embedded systems moves currently towards higher levels of abstraction. As a consequence, a need arises for an early and realistic assessment of system level design d...
ASPDAC
2004
ACM
13 years 11 months ago
2004
ACM
The design of complex systems is largely ruled by the time needed for verification. Even though formal methods can provide higher reliability, in practice often simulation based ve...
CODES
2008
IEEE
13 years 9 months ago
2008
IEEE
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
ARTS
1997
Springer
13 years 11 months ago
1997
Springer
There have been significant advances on formal methods to verify complex systems recently. Nevertheless, these methods have not yet been accepted as a realistic alternative to the ...
SRDS
2000
IEEE
14 years 17 hour ago
2000
IEEE
As has been shown, the polygon time structure overcomes the main limitations of the interval time structure, and allows to verify communication protocols, in which the explicit co...