196 search results - page 24 / 40 » Verification of timing Properties of VHDL |
FDL
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
ICECCS
1999
IEEE
13 years 12 months ago
1999
IEEE
We report on our efforts to formally specify and verify a new protocol of the E-2C Hawkeye Early Warning Aircraft. The protocol, which is currently in test at Northrop Grumman, su...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...
CHARME
2003
Springer
13 years 11 months ago
2003
Springer
Abstract. We propose new, tractably (in some cases provably) efficient algorithmic methods for exact (sound and complete) parameterized reasoning about cache coherence protocols. F...
COMPSAC
2008
IEEE
14 years 2 months ago
2008
IEEE
This work introduces probabilistic model checking as a viable tool-assisted approach for systematically quantifying DoS security threats. The proposed analysis is based on a proba...