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» Verification of timing Properties of VHDL
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EURODAC
1994
IEEE
141views VHDL» more  EURODAC 1994»
13 years 11 months ago
Exact path sensitization in timing analysis
of a direct implementation of this criterion. This paper presents the first critical path finding tool based on the exact criterion. It offers therefore better results in compariso...
R. Peset Llopis
ENTCS
2006
112views more  ENTCS 2006»
13 years 7 months ago
Patterns for Timed Property Specifications
Patterns for property specification enable non-experts to write formal specifications that can be used for automatic model checking. The existing patterns identified in [6] allow ...
Volker Gruhn, Ralf Laue
EMSOFT
2006
Springer
13 years 11 months ago
Modeling a system controller for timing analysis
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...
Stephan Thesing
EURODAC
1994
IEEE
211views VHDL» more  EURODAC 1994»
13 years 11 months ago
Advanced simulation and modeling techniques for hardware quality verification of digital systems
synchronisation also play a fundamental role in overall system robustness. ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Interference (EMI) issues also have to be conside...
S. Forno, Stephen Rochel
ICLP
2009
Springer
14 years 8 months ago
Integrating Software Testing and Run-Time Checking in an Assertion Verification Framework
Abstract. We present a framework that unifies unit testing and runtime verification (as well as static verification and static debugging). A key contribution of our overall approac...
Edison Mera, Manuel V. Hermenegildo, Pedro L&oacut...