196 search results - page 8 / 40 » Verification of timing Properties of VHDL |
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
In this paper we introduce a new knowledgebased method for planning and managing the VLSI design process, based on prediction and advice, that minimizes search in a wide design sp...
SCP
2010
13 years 2 months ago
2010
We propose a domain-specific aspect language to prevent denial of service caused by resource management. Our aspects specify availability policies by enforcing time limits in the ...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verificati...
CAV
2007
Springer
13 years 11 months ago
2007
Springer
Abstract. In this paper, we describe the features of the Timed Abstract State Machine toolset. The toolset implements the features of the Timed Abstract State Machine (TASM) langua...
FORMATS
2010
Springer
13 years 5 months ago
2010
Springer
Abstract. Quantitative verification techniques are able to establish system properties such as "the probability of an airbag failing to deploy on demand" or "the exp...