242 search results - page 13 / 49 » Verification via Structure Simulation |
DAC
2005
ACM
14 years 11 months ago
2005
ACM
In the design of highly complex, heterogeneous, and concurrent systems, deadlock detection and resolution remains an important issue. In this paper, we systematically analyze the ...
ATVA
2008
Springer
13 years 12 months ago
2008
Springer
UPPAAL PORT is a new tool for component-based design and analysis of embedded systems. It operates on the hierarchically structured continuous time component modeling language Save...
FDL
2006
IEEE
14 years 4 months ago
2006
IEEE
We present an introspection/reflection framework for SystemC which extracts design-relevant structure information and transaction data under any LRM-2.1 compliant simulation kern...
DFG
2004
Springer
14 years 1 months ago
2004
Springer
This paper presents the real-time model checker RAVEN and related theoretical background. RAVEN augments the efficiency of traditional symbolic model checking with possibilities to...
3DIC
2009
IEEE
14 years 4 months ago
2009
IEEE
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...