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» Verification via Structure Simulation
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CODES
2008
IEEE
13 years 11 months ago
Model checking SystemC designs using timed automata
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
Paula Herber, Joachim Fellmuth, Sabine Glesner
IWPSE
2010
IEEE
13 years 7 months ago
An exercise in iterative domain-specific language design
We describe our experiences with the process of designing a domain-specific language (DSL) and corresponding model transformations. The simultaneous development of the language an...
Marcel van Amstel, Mark van den Brand, Luc Engelen
DEDS
2002
97views more  DEDS 2002»
13 years 9 months ago
N-dimensional Cell-DEVS Models
This article presents an extension to the timed binary Cell-DEVS paradigm. The goal is to allow the modelling of n-dimensional generic cell spaces, including transport or inertial...
Gabriel A. Wainer, Norbert Giambiasi
CPHYSICS
2006
127views more  CPHYSICS 2006»
13 years 10 months ago
GenAnneal: Genetically modified Simulated Annealing
A modification of the standard Simulated Annealing (SA) algorithm is presented for finding the global minimum of a continuous multidimensional, multimodal function. We report resu...
Ioannis G. Tsoulos, Isaac E. Lagaris
PATMOS
2010
Springer
13 years 7 months ago
L1 Data Cache Power Reduction Using a Forwarding Predictor
In most modern processor designs the L1 data cache has become a major consumer of power due to its increasing size and high frequency access rate. In order to reduce this power con...
P. Carazo, R. Apolloni, Fernando Castro, Daniel Ch...