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» Verification via Structure Simulation
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BMCBI
2008
118views more  BMCBI 2008»
13 years 11 months ago
Inferring transcriptional compensation interactions in yeast via stepwise structure equation modeling
Background: With the abundant information produced by microarray technology, various approaches have been proposed to infer transcriptional regulatory networks. However, few appro...
Grace S. Shieh, Chung-Ming Chen, Ching-Yun Yu, Jui...
AGTIVE
2007
Springer
14 years 2 months ago
Visualization, Simulation and Analysis of Reconfigurable Systems
Meta-modeling is well known to define the basic concepts of domain-specific languages in an object-oriented way. Based on graph transformation, an abstract meta-model may be enhanc...
Claudia Ermel, Karsten Ehrig
FOAL
2009
ACM
14 years 2 months ago
Graph-based specification and simulation of featherweight Java with around advice
In this paper we specify an operational run-time semantics of Assignment Featherweight Java -- a minimal subset of Java with assignments -- with around advice, using graph transfo...
Tom Staijen, Arend Rensink
CSDA
2006
90views more  CSDA 2006»
13 years 11 months ago
Comparing two binary diagnostic tests in the presence of verification bias
The comparison of the accuracy of two binary diagnostic tests has traditionally required knowledge of the real state of the disease in all of the patients in the sample via the ap...
José Antonio Roldán Nofuentes, Juan ...
ICCAD
2006
IEEE
93views Hardware» more  ICCAD 2006»
14 years 7 months ago
Precise identification of the worst-case voltage drop conditions in power grid verification
– Identifying worst-case voltage drop conditions in every module supplied by the power grid is a crucial problem in modern IC design. In this paper we develop a novel methodology...
Nestoras E. Evmorfopoulos, Dimitris P. Karampatzak...