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ISPASS
2010
IEEE
14 years 2 months ago
Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessor
After many years of prefetching research, most commercially available systems support only two types of prefetching: software-directed prefetching and hardware-based prefetchers u...
Harold W. Cain, Priya Nagpurkar
MTV
2003
IEEE
109views Hardware» more  MTV 2003»
14 years 1 months ago
A Methodology for Validation of Microprocessors using Equivalence Checking
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Nikil D. Dutt
DAC
2007
ACM
14 years 9 months ago
Implicitly Parallel Programming Models for Thousand-Core Microprocessors
This paper argues for an implicitly parallel programming model for many-core microprocessors, and provides initial technical approaches towards this goal. In an implicitly paralle...
Wen-mei W. Hwu, Shane Ryoo, Sain-Zee Ueng, John H....
CODES
2001
IEEE
13 years 11 months ago
The TACO protocol processor simulation environment
Network hardware design is becoming increasingly challenging because more and more demands are put on network bandwidth and throughput requirements, and on the speed with which ne...
Seppo Virtanen, Johan Lilius
OSDI
2000
ACM
13 years 9 months ago
Policies for Dynamic Clock Scheduling
Pocket computers are beginning to emerge that provide sufficient processing capability and memory capacity to run traditional desktop applications and operating systems on them. T...
Dirk Grunwald, Philip Levis, Keith I. Farkas, Char...