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DSN
2007
IEEE
14 years 2 months ago
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
Christopher LaFrieda, Engin Ipek, José F. M...
KBSE
2007
IEEE
14 years 2 months ago
Ensuring consistency in long running transactions
Flow composition languages permit the construction of longrunning transactions from collections of independent, atomic services. Due to environmental limitations, such transaction...
Jeffrey Fischer, Rupak Majumdar
MTV
2007
IEEE
121views Hardware» more  MTV 2007»
14 years 2 months ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco
CLUSTER
2007
IEEE
14 years 2 months ago
Thermal-aware task scheduling for data centers through minimizing heat recirculation
— The thermal environment of data centers plays a significant role in affecting the energy efficiency and the reliability of data center operation. A dominant problem associate...
Qinghui Tang, Sandeep K. S. Gupta, Georgios Varsam...
EMSOFT
2007
Springer
14 years 2 months ago
Exploiting non-volatile RAM to enhance flash file system performance
Non-volatile RAM (NVRAM) such as PRAM (Phase-change RAM), FeRAM (Ferroelectric RAM), and MRAM (Magnetoresistive RAM) has characteristics of both non-volatile storage and random ac...
In Hwan Doh, Jongmoo Choi, Donghee Lee, Sam H. Noh