4 search results - page 1 / 1 » Verified Optimizations for the Intel IA-64 Architecture |
TPHOL
2000
IEEE
13 years 11 months ago
2000
IEEE
This paper outlines a formal model of the Intel IA-64 architecture, and explains how this model can be used to verify the correctness of assembly-level code optimizations. The form...
FMCAD
2000
Springer
13 years 11 months ago
2000
Springer
Abstract. We have formal verified a number of algorithms for evaluating transcendental functions in double-extended precision floating point arithmetic in the Intel
DAC
2000
ACM
14 years 8 months ago
2000
ACM
Contemporary microprocessors implement many iterative algorithms. For example, the front-end of a microprocessor repeatedly fetches and decodes instructions while updating interna...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
Cr, As the complexity of high-performance microprocessor increases, functional verification becomes more and more difficult and RTL simulation emerges as the bottleneck of the des...