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HVC
2007
Springer
103views Hardware» more  HVC 2007»
15 years 10 months ago
Verifying Parametrised Hardware Designs Via Counter Automata
The paper presents a new approach to formal verification of generic (i.e. parametrised) hardware designs specified in VHDL. The proposed approach is based on a translation of suc...
Ales Smrcka, Tomás Vojnar
ITC
2002
IEEE
99views Hardware» more  ITC 2002»
15 years 9 months ago
Verifying Properties Using Sequential ATPG
This paper develops a novel approach for formally verifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped int...
Jacob A. Abraham, Vivekananda M. Vedula, Daniel G....
CAISE
2006
Springer
15 years 8 months ago
Modelling and Verifying of e-Commerce Systems
Static function hierarchies and models of the dynamic behaviour are typically used in e-commerce systems. Issues to be verifies are the completeness and correctness of the static f...
Andreas Speck
CAISE
2006
Springer
15 years 8 months ago
Modeling and Verifying Workflow-based Regulations
Abstract. In this paper we present our approach to model and verify workflowintensive systems. Besides the functional properties (given by the temporal workflow description) we aug...
Daniel Fötsch, Elke Pulvermüller, Wilhel...
CCS
2006
ACM
15 years 8 months ago
An intruder model for verifying liveness in security protocols
We present a process algebraic intruder model for verifying a class of liveness properties of security protocols. For this class, the proposed intruder model is proved to be equiv...
Jan Cederquist, Muhammad Torabi Dashti